Major efforts in the development of integrated circuit semiconductor devices have been directed towards decreasing the size and spacing of the devices and towards efficiently fabricating different families of devices on the same semiconductor chip. Extensive efforts, for example, have been directed towards the manufacture of BICMOS logic which includes both bipolar and complementary metal-oxide semiconductor devices on the same semiconductor chip. For such BICMOS logic to be successful, it must be capable of efficient manufacture, i.e. not require too many complex or expensive processing steps. Further, the finished logic circuit must provide small, densely packed, high performance devices.
One method of manufacturing semiconductor devices to provide smaller device size and decreased device spacing is that known as "lost wax" or "reverse image" processing. In such processes, a protective structure such as a stud or ridge is formed on a silicon wafer. Doping and/or various other process are performed using the protective structure as a mask. The structure is subsequently removed in the final steps of the process. Examples of such a method include: U.S. Pat. No. 4,571,817 to Birritella et al.; European Patent Application EP 0 128 751 by Toshiba; and J. Jiyamoto et al. "A 1.0 Micron N-Well CMOS/Bipolar Technology for VLSI Circuits", IEDM 1983, pgs 63-66.
The following are of interest as directed towards the manufacture of BICMOS devices: U.S. Pat. No. 4,299,024 to Piotrowski; U.S. Pat. No. 4,475,279 to Gahle; U.S. Pat. No. 4,507,847 to Sullivan; U.S. Pat. No. 4,484,388 to Iwasaki; U.S. Pat. No. 4,637,125 to Iwasaki et al.; U.S. Pat. No. 4,486,942 to Hirao; F. Walczyk, J. Rubinstein, "A Merged CMOS/Bipolar VLSI Process", IEDM 1983, pgs. 59-62; H. Higuchi et al., "Performance and Structures of Scaled-Down Bipolar Devices Merged with CMOSFETS", IEDM 1984, pgs. 684-687.
U.S. Pat. No. 4,419,809 to Riseman et al., assigned to the assignee of the present invention, uses the above-described "lost wax" method to form the drain region of a MOSFET. Riseman et al. further shows the use of sidewall technology to form a sub-micron device channel.
U.S. Pat. No. 4,508,579 to Goth et al., assigned to the assignee of the present invention, shows a method of forming lateral device structures using insulating studs formed from oxide sidewalls.
U.S. Pat. No. 4,160,991 to Anantha et al., assigned to the assignee of the present invention shows a method of forming high performance bipolar transistors having closely spaced base-emitter contacts.
In summary, a process which yields semiconductor devices having smaller or more closely spaced device regions provides a substantial contribution to the art. Such a process is of even greater value if it can be economically and efficiently implemented, particularly with different device types.